The development of relatively complex microchips has caused microchip designer's to implement test functionality and test devices within the microchips themselves. The built-in-self-test functions are based on several design-for-test (DFT) techniques such as a (i) logic built-in self-test (LBIST) method for testing combinatorial and sequential logic devices, and (ii) array built-in-self- test (ABIST) for testing memory arrays.
Generally, during the built-in self-testing (BIST) of a microchip, a linear feedback shift register (LFSR) on the chip generates a sequence of pseudo-random binary test data which will be used to stimulate the combinatorial or sequential logic devices or memory arrays in the microchip. The test data is clocked into the combinatorial or sequential logic devices, or memory arrays and the output data received from the devices or memory arrays is clocked into a multiple input shift register (MISR) which compresses the data over multiple test data cycles. After the received response data from the devices is compressed over a predetermined number of test cycles, a “signature” value is obtained from the MISR. The signature value is thereafter compared to a desired signature value to determine if any of the combinatorial or sequential logic devices, or memory arrays failed the test sequence.
Further, to test multiple sets of devices on a microchip a plurality of MISR's may be utilized which produce a plurality of signature values during testing. Further, as discussed above each signature value is compared to a predetermined “pass” signature value to determine whether each set of devices associated with the MISR operated correctly. The comparison of the plurality of MISR signatures with a plurality of “pass” signatures can take relatively large amounts of computational effort, time, and additional comparison circuitry components. The inventors herein have thus recognized that there is a need for a simplified system and method for testing combinatorial logic devices, sequential logic devices, and memory arrays in microchips that eliminates the step of comparing the plurality of MISR signatures with the plurality of “pass” signatures to determine whether any of the plurality of sets of devices failed testing.